The PowerShrink technology from SuVolta comes as a breath of fresh air in a world that has been enamored by new mobile operating systems and applications while improvements in core technology seem to have been slowing down. PowerShrink looks to get the momentum rolling again by improving core technology that is specifically related to special transistors that perform voltage scaling for the CPU in a unique way and reducing leakage, which is a problem when chips can have over 1 billion transistors.
The main focus for PowerShrink is 65nm technologies (1nm is one billionth of a meter) where independent testing by Fujitsu Semiconductor verified their claims of decreasing power consumption by 50% without impacting performance and reducing power lost from leakage by 5 times more than current leakage reduction technology. That's quite a thing since everyone stands to gain from improvements in hardware efficiency.
The specialized transistor that makes PowerShrink technology work is their Deeply Depleted Channel CMOS transistor, which leverages their unique design as shown in the image above. It focuses on eliminating voltage variation within the transistor by 50% and allows 30% scaling of the supply voltage, which means it could actually reduce power consumption by up to 80% without reducing performance. How about them apples? The cherry on top is that we will probably see this technology being licensed out and implemented into shiny new devices sometime in 2012. This is because, for hardware manufacturers to adopt SuVolta's DDC, they can use their existing equipment and not drop millions upon millions into research, equipment and facilities. Personally, I hope to see a lot more of this in the future.